The present invention relates to ferroelectric memory devices using ferroelectric capacitors in memory cells thereof and to methods for reading data from the same. More specifically, the present invention relates to a ferroelectric memory device in which a reference potential is generated by two reference cells retaining different data, and to a method for reading data from the same.
Recently, developments of ferroelectric memory devices have been proceeding. The ferroelectric memory device uses as memory elements ferroelectric capacitors having capacitor insulating films of ferroelectric, and retains data by utilizing remnant polarization held in the ferroelectric. Heretofore, the ferroelectric memory device has generally employed as a memory cell a two-transistor, two-capacitor memory cell which retains complementary data in two ferroelectric capacitors by using two transistors. Because of a recent demand for an increased data capacity and a recent trend toward a miniaturized process technology, the ferroelectric memory device has alternatively applied a one-transistor, one-capacitor memory cell.
The one-transistor, one-capacitor memory cell is provided with one bit line pair for reading data. Of the bit line pair connected to the memory cell, one bit line is supplied with a reference potential (reference level) and the other bit line is supplied with a potential according to remnant polarization. The potential difference across the two bit lines is then amplified by a sense amplifier, whereby data reading for the memory cell is performed. For example, Japanese Unexamined Patent Publication No.7-262768 discloses an exemplary one-capacitor, one-transistor memory cell of this type in which a reference potential is generated by two reference cells retaining different data.
A conventional ferroelectric memory device employing the one-transistor, one-capacitor memory cells will be described below with reference to the accompanying drawings.
FIG. 9 shows a circuit configuration of the conventional ferroelectric memory device. Referring to FIG. 9, the conventional ferroelectric memory device includes, as memory cells for retaining data, first to fourth memory cells 101 to 104 composed of transistors T1 to T4 and ferroelectric capacitors C1 to C4, respectively.
In the transistors T1 to T4, gates are each connected to either of word lines WL1 and WL2, and drains are connected to bit lines BL1 to BL4, respectively. In the ferroelectric capacitors C1 to C4, first electrodes are connected to sources of the transistors T1 to T4, respectively, and second electrodes are each connected to either of cell plate lines CP1 and CP2.
The conventional ferroelectric memory device further includes, as memory cells for retaining data used in the generation of a reference potential, first to fourth reference cells 105 to 108 composed of transistors T5 to T8 and ferroelectric capacitors C5 to C8, respectively.
In the transistors T5 to T8, gates are each connected to either of reference word lines RWL1 and RWL2, and drains are connected to the bit lines BL1 to BL4, respectively. In the ferroelectric capacitors C5 to C8, first electrodes are connected to sources of the transistors T5 to T8, respectively, and second electrodes are each connected to either of reference cell plate lines RCP1 and RCP2.
The first to fourth reference cells 105 to 108 are provided with first to fourth reset circuits 109 to 112, respectively, as circuits for writing predetermined pieces of data in the respective cells. The first to fourth reset circuits 109 to 112 are composed of transistors T9 to T12 whose drains are connected to the first electrodes of the ferroelectric capacitors C5 to C8, respectively.
The first and third bit lines BL1 and BL3 are connected to each other through a first switch circuit 113 composed of a transistor T13. The second and fourth bit lines BL2 and BL4 are connected to each other through a second switch circuit 114 composed of a transistor T14.
The first and second bit lines BL1 and BL2 are both connected to a first precharge circuit 115 composed of two transistors T15 and T16, and also connected to a first sense amplifier 116. The first and second bit lines BL1 and BL2 serve as a bit line pair for the first sense amplifier 116. Likewise, the third and fourth bit lines BL3 and BL4 are both connected to a second precharge circuit 117 composed of two transistors T17 and T18, and also connected to a second sense amplifier 118. The third and fourth bit lines BL3 and BL4 serve as a bit line pair for the second sense amplifier 118.
The ferroelectric memory device further includes a control circuit 119 for controlling the circuits described above. To be more specific, the control circuit 119 drives the first word line WL1, the second word line WL2, the first cell plate line CP1, the second cell plate line CP2, the first reference word line RWL1, the second reference word line RWL2, the first reference cell plate line RCP1, and the second reference cell plate line RCP2. Further, the control circuit 119 controls actions performed by each memory cell and each reference cell.
The control circuit 119 controls the first and third reset circuits 109 and 111 with a first reset control signal RPG1, the second and fourth reset circuits 110 and 112 with a second reset control signal RPG2, the first switch circuit 113 with a first switch control signal REQ1, the second switch circuit 114 with a second switch control signal REQ2, the first and second precharge circuits 115 and 117 with a precharge signal BP, and the first and second sense amplifiers 116 and 118 with a sense amplifier driving signal SAE.
The read operation in the conventional ferroelectric memory device will be described below with reference to the accompanying drawing. The following description using FIG. 10 is about the case where data is read out of the first and third memory cells 101 and 103, provided that the first and third memory cells 101 and 103 retain “1” data and “0” data, respectively, and the second and fourth reference cells 106 and 108 retain “1” data and “0” data, respectively.
Note that the memory cells and the reference cells retain “1” data when the ferroelectric capacitors C1 to C8 thereof have remnant polarization with their first electrodes being positive electrodes, and that they retain “0” data when the ferroelectric capacitors C1 to C8 thereof have remnant polarization with their second electrodes being positive electrodes.
FIG. 10 shows timings of the read operation in the conventional ferroelectric memory device. As shown in FIG. 10, first, in the initial state of the reading operation in this device, the bit line precharge signal BP is activated (a logical voltage of “H” level). The activated signal drives the first and second precharge circuits 115 and 117 to precharge the corresponding bit lines (specifically, the first, second, third and fourth bit lines BL1, BL2, BL3 and BL4) at the ground voltage Vss. In this state, the first word line WL1, the first cell plate line CP1, the second reference word line RWL2, the second reference cell plate line RCP2, the second switch control signal REQ2, the second reset control signal RPG2, the reset data signal RPD, and the sense amplifier driving signal SAE stay inactivated (a logical voltage of “L” level).
Next, the bit line precharge signal BP is inactivated at the timing of time t1, whereby the bit lines BL1 to BL4 are made floating.
Then, at the timing of time t2, the second switch control signal REQ2, the first word line WL1, the first cell plate line CP1, the second reference word line RWL2, and the second reference cell plate line RCP2 are activated.
In response, the transistors T1 and T3 are turned on and a voltage of “H” level is applied to the second electrodes of the ferroelectric capacitors C1 and C3. Then, “1” data retained in the first memory cell 101 is supplied to the first bit line BL1 and “0” data retained in the third memory cell 103 is supplied to the third bit line BL3. In addition, the transistors T6 and T8 are turned on and a voltage of “H” level is applied to the second electrodes of the ferroelectric capacitors C6 and C8. Then, “1” data retained in the second reference cell 106 is supplied to the second bit line BL2 and “0” data retained in the fourth reference cell 108 is supplied to the fourth bit line BL4.
At this timing, the activated second switch control signal REQ2 drives the second switch circuit 114 to equalize the second and fourth bit lines BL2 and BL4. As a result, the second and fourth bit lines BL2 and BL4 are supplied with an intermediate potential between the potential corresponding to “1” data and the potential corresponding to “0” data, which serves as a reference potential (reference level).
Next, at the timing of time t3, the first cell plate line CP1 and the second reference cell plate line RCP2 are inactivated.
Then, at the timing of time t4, the sense amplifier driving signal SAE is activated to drive the first and second sense amplifiers 116 and 118. In response, a potential difference across the first and second bit lines BL1 and BL2 is amplified so that the voltage value of the first bit line BL1 is equal to the source voltage Vcc and the voltage value of the second bit line BL2 is equal to the ground voltage Vss. Simultaneously, a potential difference across the third and fourth bit lines BL3 and BL4 is amplified so that the voltage value of the third bit line BL3 is equal to the ground voltage Vss and the voltage value of the fourth bit line BL4 is equal to the source voltage Vcc.
At this timing, the first word line WL1 stays activated, so that the source voltage Vcc and the ground voltage Vss are supplied to the first electrodes of the ferroelectric capacitors C1 and C3 through the transistors T1 and T3, respectively. Thus, rewriting in the first and third memory cells 101 and 103 is performed.
Subsequently to this series of actions, the second reference word line RWL2 and the second switch control signal REQ2 are successively inactivated. In response, the transistors T6 and T8 are turned off to separate the second and fourth reference cells 106 and 108 from the second and fourth bit lines BL2 and BL4, respectively, after which the second switch circuit 114 is stopped to separate the second bit line BL2 from the fourth bit line BL4.
Next, the reset data signal RPD and the second reset control signal RPG2 are successively activated, thereby performing rewriting in the second and fourth reference cells 106 and 108 by using the second and fourth reset circuits 110 and 112. In this rewriting, the first electrode of the ferroelectric capacitor C8 of the fourth reference cell 108 is supplied with the ground voltage Vss, so that “0” data is written in the fourth reference cell 108. On the other hand, the first electrode of the ferroelectric capacitor C6 of the second reference cell 106 is supplied with a voltage of “H” level serving as the reset data signal RPD, so that “1” data is written in the second reference cell 106.
Next, at the timing of time t5, the sense amplifier driving signal SAE is inactivated to stop the drive of the first and second sense amplifiers 116 and 118, after which the second reference cell plate line RCP2 is activated. In response, of the electrodes of the ferroelectric capacitor C6 of the second reference cell 106, the first electrode is supplied with a voltage of “H” level derived from the reset data signal RPD, and the second electrode is supplied with a voltage of “H” level derived from the second reference cell plate line RCP2. Therefore, the voltage applied to the ferroelectric capacitor C8 of the fourth reference cell 108 becomes zero volts.
Thereafter, the bit line precharge signal BP is activated and in addition the second reference cell plate line RCP2, the first word line WL1, the reset data signal RPD, and the second reset control signal RPG2 are successively inactivated to restore the device condition to the initial state. The read operation of the device is thus completed.
Next description using the drawings will be made of changes in charges stored in the ferroelectric capacitors during the read operation in the conventional ferroelectric memory device.
FIG. 11 is a graph showing the hysteresis properties of ferroelectric used in the ferroelectric capacitors of the conventional ferroelectric memory device. FIG. 11 plots the voltage applied to the electrodes of each ferroelectric capacitor in abscissa and the polarization charge thereof in ordinate. In FIG. 11, a positive polarization charge represents the amount of the polarization charge in the case where the first electrodes of the ferroelectric capacitors C1 to C8 are used as positive electrodes.
As shown in FIG. 11, when the source voltage Vcc in the positive direction is applied to a ferroelectric capacitor, the capacitor stores a polarization charge corresponding to a point A. When the applied voltage is changed from this state in the negative direction, the ferroelectric capacitor stores a polarization charge corresponding to a point to which the point A moves along a curve 131 in the negative direction. In contrast, when the source voltage Vcc in the negative direction is applied to the ferroelectric capacitor, the capacitor stores a polarization charge corresponding to a point B. When the applied voltage is changed from this state in the positive direction, the ferroelectric capacitor stores a polarization charge corresponding to a point to which the point B moves along a curve 132 in the positive direction.
The following description using FIG. 11 is about changes (the movement on FIG. 11) in polarization conditions of the ferroelectric capacitors in accordance with the timings of the read operation shown in FIG. 10.
Note that “L” level in FIG. 10 is set at the ground potential value Vss (0 V) and “H” level in FIG. 10 is set at the source voltage value Vcc.
First, at the timing of the time to in FIG. 10, no voltage is applied to the ferroelectric capacitors C1 to C8 of the memory cells and the reference cells. Therefore, in the first memory cell 101 and the second reference cell 106 both of which retain “1” data, the polarization charges of the ferroelectric capacitors C1 and C6 are located at a point C in FIG. 11. In the third memory cell 103 and the fourth reference cell 108 both of which retain “0” data, the polarization charges of the ferroelectric capacitors C3 and C8 are located at a point D in FIG. 11.
At the timing of the time t2 in FIG. 10, the transistors T1 and T3 are turned on and the source voltage Vcc is applied to the first cell plate line CP1. Then t2, the ground voltage Vss is applied to the first electrodes of the ferroelectric capacitors C1 and C3 and the source voltage Vcc is applied to the second electrodes of the ferroelectric capacitors C1 and C3. Likewise, the transistors T6 and T8 are turned on and the source voltage Vcc as a voltage of “H” level is applied to the second reference cell plate line RCP2. Then the ground voltage Vss is applied to the first electrodes of the ferroelectric capacitors C6 and C8 and the source voltage Vcc is applied to the second electrodes of the ferroelectric capacitors C6 and C8. Each of the ferroelectric capacitors C1, C3, C6 and C8 then changes in the condition from the state in which no voltage is applied to the state in which a negative voltage (−Vcc) is applied thereto.
At this timing, in the first memory cell 101, the polarization charge of the ferroelectric capacitor C1 moves from the point C to a point E along the curve 131. The point E is placed at the point determined by dividing the voltage Vcc applied to the ferroelectric capacitor C1 in accordance with the capacitance of the first bit line BL1 and the capacitance of the ferroelectric capacitor C1. To be more specific, the point to which the point C moves along the voltage axis in the negative direction by the voltage Vcc is defined as a point F, and a capacitance load line 133a of the first bit line BL1 is drawn from the point F. Thus, the point E is obtained as the intersection point of the capacitance load line 133a with the curve 131.
In the third memory cell 103, the polarization charge of the ferroelectric capacitor C3 moves from the point D along the curve 132 in the negative direction, and reaches to a point H which is located at the intersection point of the curve 132 with a capacitance load line 133c of the third bit line BL3 drawn from a point G to which the point D moves along the voltage axis in the negative direction by the voltage Vcc. Note that the capacitance of the third bit line BL3 is equal to that of the first bit line BL1, so that the capacitance load line 133c of the third bit line BL3 has the same inclination as the capacitance load line 133a of the first bit line BL1.
Likewise, in the second reference cell 106, the polarization charge of the ferroelectric capacitor C6 moves from the point C to a point I, and in the fourth reference cell 108, the polarization charge of the ferroelectric capacitor C8 moves from the point D to a point J. Herein, the point I is located at the intersection point of the curve 131 with a capacitance load line 134a of the second bit line BL2. The capacitance load line 134a has a greater inclination than the capacitance load lines 133a and 133c because the second and fourth bit lines are equalized to increase the capacitance value of the second bit line.
At this timing, a charge Q3 is read out on the first bit line BL1, and the first bit line BL1 has a potential of “1” data corresponding to the point E. Also, a charge Q2 is read out on the second and fourth bit lines BL2 and BL4, and the second and fourth bit lines BL2 and BL4 have reference potentials corresponding to the points I and J. Further, a charge Q1 is read out on the third bit line BL3, and the third bit line BL3 has a potential of “0” data corresponding to the point H. As a result, a potential difference V1 is created across the first and second bit lines BL1 and BL2, and a potential difference V2 is created across the third and fourth bit lines BL3 and BL4.
Next, at the timing of the time t3 in FIG. 10, the first cell plate line CP1 and the second reference cell plate line RCP2 are inactivated, so that in the first memory cell 101, the third memory cell 103, the second reference cell 106, and the fourth reference cell 108, the voltages applied to the respective ferroelectric capacitors change from the negative voltage (−Vcc) to zero volts.
By this change, in the first memory cell 101, the polarization charge of the ferroelectric capacitor C1 moves from the point E to a point K along a curve 135. The point K is located at the intersection point of the curve 135 with a capacitance load line 133b of the third bit line BL1 drawn from a point L to which the point E moves along the voltage axis in the positive direction by the voltage Vcc. In the third memory cell 103, the polarization charge of the ferroelectric capacitor C3 moves from the point H to the point D along the curve 132.
Likewise, in the second reference cell 106, the polarization charge of the ferroelectric capacitor C6 moves from the point I to a point M along a curve 136. The point M is located at the intersection point of the curve 136 with a capacitance load line 134b of the second bit line BL2 drawn from a point N to which the point I moves along the voltage axis in the positive direction by the voltage Vcc. In the fourth reference cell 108, the polarization charge of the ferroelectric capacitor C8 moves from the point H to a point P along the curve 132.
At that time, a potential difference V3 corresponding to the potential difference across the points K and P is created across the first and second bit lines BL1 and BL2, and a potential difference V4 corresponding to the potential difference across the points D and P is created across the third and fourth bit lines BL3 and BL4.
Next, at the timing of the time t4 in FIG. 10, the potential difference V4 is amplified by the first sense amplifier 116, whereby the first bit line BL1 has the source voltage Vcc and the second bit line BL2 has the ground voltage Vss. Since the transistors T1 and T6 are on in this state, the ferroelectric capacitor C1 of the first memory cell 101 has a positive voltage (Vcc) applied and the ferroelectric capacitor C6 of the second reference cell 106 has a voltage of zero volts. Therefore, in the first memory cell 101, the polarization charge of the ferroelectric capacitor C1 moves from the point K to the point A along the curve 135. In the second reference cell 106, the polarization charge of the ferroelectric capacitor C6 moves from the point M to a point Q.
Likewise, the potential difference V3 is amplified by the second sense amplifier 118, whereby the third bit line BL3 has the ground voltage Vss and the fourth bit line BL4 has the source voltage Vcc. Since the transistors T3 and T8 are on in this state, the ferroelectric capacitor C3 of the third memory cell 103 keeps a voltage of zero volts and the polarization charge thereof does not move and remains at the point D. In the fourth reference cell 108, the ferroelectric capacitor C8 thereof has the source voltage Vcc applied, so that the polarization charge thereof moves from the point P to the point A.
Subsequently, the reset data signal RPD and the second reset control signal RPG2 are successively activated. Then, the source voltage Vcc derived from the reset data signal RPD is applied to the first electrode of the ferroelectric capacitor C6 of the second reference cell 106, and the ground voltage Vss is applied to the ferroelectric capacitor C8 of the fourth reference cell 108. Therefore, the voltage applied to the ferroelectric capacitor C6 is changed from zero volts to a positive voltage and the polarization charge thereof moves from the point Q to the point A along the curve 136. In the ferroelectric capacitor C8 of the fourth reference cell 108, the voltage applied to the ferroelectric capacitor C8 is changed from the source voltage Vcc to zero volts and the polarization charge thereof moves from the point A to the point C along the curve 131.
Next, the second reference cell plate line RCP2 is activated subsequently to the timing of the time t5 in FIG. 10, whereby the source voltage Vcc is applied to the second electrodes of the ferroelectric capacitors C6 and C8 of the second and fourth reference cells 106 and 108. The voltage applied to the ferroelectric capacitor C6 is then changed from a positive voltage to zero volts and the polarization charge thereof moves from the point A to the point C along the curve 131. On the other hand, the voltage applied to the ferroelectric capacitor C8 is then changed from zero volts to a negative voltage and the polarization charge thereof moves from the point C to the point B along the curve 131.
Thereafter, the reset data signal RPD and the second reset control signal RPG2 are successively inactivated, so that the voltages of the first electrodes of the ferroelectric capacitors C6 and C8 become zero volts. The second reference cell plate line RCP2 is inactivated, so that the voltages of the second electrodes of the ferroelectric capacitors C6 and C8 become zero volts. From these actions, the ferroelectric capacitor C6 of the second reference cell 106 keeps a voltage of zero volts and the polarization charge thereof remains at the point C. In the fourth reference cell 108, the voltage applied to the ferroelectric capacitor C8 is then changed from a negative voltage to zero volts and the polarization charge thereof moves from the point B to the point D along the curve 132.
As is apparent from the above, the read operation of the memory cells in the conventional ferroelectric memory device is accomplished so that in the memory cell retaining “1” data, the polarization charge of the ferroelectric capacitor thereof moves progressively in the order of the point C, the point E, the point K, the point A, and the point C, and that in the memory cell retaining “0” data, the polarization charge of the ferroelectric capacitor thereof moves progressively in the order of the point D, the point H, the point B, and the point D. The read operation of the reference cells is accomplished so that in the reference cell retaining “1” data, the polarization charge of the ferroelectric capacitor thereof moves progressively in the order of the point C, the point I, the point M, the point Q, the point A, and the point C, and that in the reference cell retaining “0” data, the polarization charge of the ferroelectric capacitor thereof moves progressively in the order of the point D, the point J, the point P, the point A, the point B, and the point D. In this read operation, the amount of charge for polarization reversal in the ferroelectric capacitor retaining “0” data is equal to the charge amount QSW between the point C and the point D shown in FIG. 11.
The conventional ferroelectric memory device described above, however, has a problem relating to the properties of the number of rewriting operations. In a number of memory cells provided on a single bit line pair, every time one memory cell is read out, one reference cell pair operates for the reading. This greatly increases the number of times each reference cell operates as compared with the number of times each memory cell operates. As a result, the properties of the number of rewriting operations in the ferroelectric memory device decrease depending upon the degradation of the reference cells.